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Altera_Forum's avatar
Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

As FPGAs and CPLDs can only work on a single clock edge, you'll need a clock frequency of 297Mhz. I dont think a CPLD will be able to do that for you..