CPLD Max II Safe Clock division

In the MaxII architecture that is about the only way to do it. 100MHz clock comes in on a clock pin, distribute and use as CLK100. Use that to clock a divide by 2 FF to generate signal CLK50, and use that as the clock for your 50MHz logic. Quartus will assign CLK100 and CLK50 to high fanout, low skew routing. The on CLK50 register the signals that you want to drive DIRECTLY to the output pin nodes. This will give you the fastest clock to output delay. Drive outputs directly, don't add any logic functions (and, or, etc) between the register outputs and the output pins. And as I said add timing constraints to the design to guide Quartus layout, and validate that your device will meet your timing requirements.

BTW the MaxII is a REALLY old family at this point. It should NOT be used in any new design, but only if you are reusing some existing legacy boards.