Forum Discussion
MFric2
New Contributor
New ContributorCPLD Max II Safe Clock division
Hey guys, what is a safe way to realize the behaviour in the picture below without using a PLL (because there is none in MAX II device).... Should i generate a Clock enable ? How do i do this reali...
MFric2New Contributor
New ContributorHey thanks for your answer so far. The 100 Mhz are from an external oscillator crystal and feed into one of the dedicated clock inputs of the CPLD, i need to divide this clock to 50 Mhz in the CPLD to use it as clock source for another external device.... is this possible in any reliable way ?
... Actually while iam writing this and think about it there might be no really reliable way to do this without PLL :/ but maybe iam wrong.
