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MFric2
New Contributor
New ContributorCPLD Max II Safe Clock division
Hey guys, what is a safe way to realize the behaviour in the picture below without using a PLL (because there is none in MAX II device).... Should i generate a Clock enable ? How do i do this reali...
ak6dn
Regular Contributor
Regular ContributorYou really don't provide enough background info for a detailed answer. How are the clocks for the 100MHz and 50MHz domains generated?
To meet some external timing constraints you should write constraints for the layout that express your restrictions and then Quartus will attempt to meet these and it will tell you if it can't in the timing report.
