Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

CPLD EPM570 outputs to VDD after programming

Hello everybody,

I am running into a fairly strange phenomenon in which I try and

program a CPLD, and although I can see my debug pins in my top level

bdf file as being there, they are also shown in the .pin file, all pins are tied to VDD when I measure with an oscope after programming the device.

Thus my question - how can I verify the contents of my programming configuration (pof) file ? I have also delted it and regenerated, strange that

I can program the CPLD but not get outputs on my debug pins.

Thanks a bunch -

Eric

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hello everybody,

    I am running into a fairly strange phenomenon in which I try and

    program a CPLD, and although I can see my debug pins in my top level

    bdf file as being there, they are also shown in the .pin file, all pins are tied to VDD when I measure with an oscope after programming the device.

    Thus my question - how can I verify the contents of my programming configuration (pof) file ? I have also delted it and regenerated, strange that

    I can program the CPLD but not get outputs on my debug pins.

    Thanks a bunch -

    Eric

    --- Quote End ---

    Hi Eric,

    look into the reports of your compile run. Did you get messages like pin xxxx stuck at VCC ?

    Did you run simulation in order to make sure that your design behaves at intended ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    In addition, are the pins stuck to VCCIO or have default weak pull-up (unconfigured state).