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Altera_Forum
Honored Contributor
Honored ContributorCPLD CLock divider?
I have been a long time MAX user. In the old days when I needed to divide a clock I would just use the counter output to drive the clock input of my destination flip flop. This always worked well in ...
Altera_ForumHonored Contributor
Honored ContributorThere are timing reasons that make it always better to use a clock enable instead of a divided clock. However, it might be a lot of trouble to change existing source files to use the clock enable for many destinations, and the paths driven by the clock enable will have to run in a single clock cycle. My post at "Altera Forums > Tools Related > Quartus II Discussion > PLL Clock Frequency" describes a case where it is OK to use a divided clock.
