counter VHDL

hi,

i am trying to make a counter using the 50Mhz clock on my board DE1,

when i

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY teller IS
    PORT (
 
        clock : IN STD_LOGIC:='1';
        output1 : buffer STD_LOGIC;
    output2 : buffer STD_logic
    );
END teller;
ARCHITECTURE BEHAVIOR OF teller IS
signal counter: integer range 0 to 50000000;
begin
 
 output2<=clock;
 process(clock)
 begin
  if(rising_edge(clock)) then
   if counter =50000000 then
    output1<= not output1;
    counter<=1;
   else
    counter<=counter +1;
   end if;
  end if;
 end process;
END BEHAVIOR;

the output2led is half output power, but the out 1 led should flash +- 2/sec. but the led is always on. when i set the counter range to 5 and connect the clock to a pushbutton, it counts and at 5 the led turns of and on after 10....

why doesn't it work on the 50Mhz clock?

thanks

jeffrey