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Altera_Forum's avatar
Altera_Forum
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15 years ago

Converting from AHDL to Verilog

Hi,

After 15 years of writting AHDL programs, I am switching to Verilog. In

my AHDL programs I normally have the "top" or "main" program contain

the include statements , then I/O pin assignments, and finally I/O

port assignments for the many lower modules. There is usually no logic in the top

level file. I have read many books and tutorials but have not found a good

example on how to create this structure in Verilog. Is this the right approach for

doing hierarchical design in Verilog. Any tips or examples would be appreciated.

Thanks!!!!!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    Parameter is optional literal for readability to be used locally inside the design instead of directly embedding numbers (dec/binary or octal or hex) for example.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks a lot! A quick question, if "module my_design (a,b,c,d)" is the top level why does it have parameter after it? thanks again!:confused:

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I did verilog ages ago, I used the following template, I hope it will help but may need considerable updating: 

    
 // A sample Verilog program structure
‘include “file1.v”                  // lower module macro
‘define “my_line” 16’hBB7F     // line macro 
//design IF
module my_design (a,b,c,d)
input  a,b;  //direction,width,name
input c;
output  d;
//internal design declarations
//
reg  d;                      //output registered
wire w1,w2                       //for instantiation or node wiring   
integer  I;                      //general use e.g. loop index
parameter k = 4’b1             //literal 
‘include “file2.v”                //macro replacement 
function f1;
input a;
parameter k = 8’10001110”;
integer n; 
begin    
    Sequential statements...
end
endfunction 
task t1;
input a;
output b;
parameter k = ‘8b11110000”; 
begin    
    Sequential statements...
end
endtask 
//start of design
//instantiations
Lower_mod1# (5,8) mod_1(w1,w2);       //positional association
Lower_mod2 mod2 ( 
                         .a    (w1),                
                         .b    ()                 
                           );                        //named association 
//wiring
assign w3 = ~(a & b);         //continuous assignment 
//intial values
initial begin
...
end
 //seq like process of vhdl
always @ (a or b) begin       
...     
end 
endmodule