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Altera_Forum
Honored Contributor
Honored ContributorConverting from AHDL to Verilog
Hi, After 15 years of writting AHDL programs, I am switching to Verilog. In my AHDL programs I normally have the "top" or "main" program contain the include statements , then I/O pin assign...
Altera_ForumHonored Contributor
Honored ContributorThanks a lot! A quick question, if "module my_design (a,b,c,d)" is the top level why does it have parameter after it? thanks again!:confused:
