Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Controlling Burst Mode in software

Hi. I have a verilog module that buffers a considerable amount of samples and when the buffer gets full id like to empty the buffer using a Nios processor for some computations. Using single IOR istr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks so much!!! U helped me a lot!!!!! Thanks again!!!!!!!!!!!!!!!!!!!!!!!:)