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Altera_Forum
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17 years ago

Contraints Query

Hi All, I have a design which is purely combo. The logic is given below, first_out <= fixed and inputA; sec_out <= fixed and inputB; third_out <= fixed and inputC; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanx jms for your reply.

As i mentioned in the code, the output from module is logical and of two input signals.

So here i have two constrain set_max_delay for both these inputs right ?

I mean if the combo is

Outp <= inpA and inpB;

The constrain would be,

set_max_delay -from {inpa} -to {outp} <value>

set_max_dealy -from {inpb} -to {outp} <value>

Please confirm.

regards,

freak