Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Contraints Query

Hi All,

I have a design which is purely combo.

The logic is given below,

first_out <= fixed and inputA;

sec_out <= fixed and inputB;

third_out <= fixed and inputC;

temp_output <= inputA and ext_input;

Here inputA, inputB, inputC are module inputs where inputA is asynch input and other two are synch inputs. The input fixed is coiming in synch from an external module.

The three outputs first_out , sec_out and third_out are outputs going from my module to different IP. Similarly temp_output is also an output from my module.

Here, how we constrain this inputs and outputs. Do we need to specify input and output delay here since, there is no sequential logic in my module using these input signals.

Please share ur ideas.

Best Regards.

freak

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Yep, that's right freak.

    If the paths are identical, you can use a single constraint

    set_max_delay -to {Outp} <value>

    without -from specified, this means "every path that goes to Outp".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thanx jms for your reply.

    As i mentioned in the code, the output from module is logical and of two input signals.

    So here i have two constrain set_max_delay for both these inputs right ?

    I mean if the combo is

    Outp <= inpA and inpB;

    The constrain would be,

    set_max_delay -from {inpa} -to {outp} <value>

    set_max_dealy -from {inpb} -to {outp} <value>

    Please confirm.

    regards,

    freak
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Use set_max_delay -from [all_inputs] -to [all_outputs] 10.000. Replace 10.000 by the delay you need.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi v.f.,

    If your design is purely combinatorial, and the clocked logic is in other external devices, then you need to use constraints that don't refer to clocks, like set_max_delay, set_min_delay. set_input_delay and set_output_delay only have meaning in relation to clocks.

    I think you have something like this:

    (inputB source) -> your module -> (sec_out destination)

    if the inputB source and the sec_out destination use the same clock, then you would determine tCO from source, tSU at destination, and any board delays. Then you would constrain the path through your module to be less than the remaining time:

    set_max_delay -to sec_out PERIOD-tCO-tSU-tPD

    IF your source and destination are in the same FPGA, just different RTL modules, then you don't really need to constrain the paths through each individual module -- the Quartus tools will only need to know the clock period and will know the paths from source to destination must be shorter than the period.

    Does that help ?