Contraints Query

Hi v.f.,

If your design is purely combinatorial, and the clocked logic is in other external devices, then you need to use constraints that don't refer to clocks, like set_max_delay, set_min_delay. set_input_delay and set_output_delay only have meaning in relation to clocks.

I think you have something like this:

(inputB source) -> your module -> (sec_out destination)

if the inputB source and the sec_out destination use the same clock, then you would determine tCO from source, tSU at destination, and any board delays. Then you would constrain the path through your module to be less than the remaining time:

set_max_delay -to sec_out PERIOD-tCO-tSU-tPD

IF your source and destination are in the same FPGA, just different RTL modules, then you don't really need to constrain the paths through each individual module -- the Quartus tools will only need to know the clock period and will know the paths from source to destination must be shorter than the period.

Does that help ?