Contraining source synchronous interfaces

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Ok, but why is then setup relationship=0ns at the FPGA input?

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At the FPGA io you can play some games to achieve timing.

option 1: usual default behavior i.e. latch on next edge

option 2: same edge launch/latch; if that helps timing

No 2 is possible because as long as data stream is sampled correctly it doesn't matter if delay or advance is introduced. In this case the fitter will see if it is achievable or not.