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Honored Contributor
Honored ContributorConstraints from LVDS blocks and logic
Hi,
I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using clocks from a PLL. TimingQuest gives me an erro and show the sclkout rising edge as the source clock but with the rising edge of the register clock directly underneath. I've used the write sdc command and got the lvds constraints it generates. However, they just don't seem to cover this path between the sclkout and the registers. I would have though that the hold time would have been 4 sclks. I do have a clock mux on a couple of outputs from the PLL and it's the output of the mux that drives the registers. I don't know if this is cause a problem or not. If I put a hold time of 2, then problem goes away but is TimingQuest highlighting a problem? Regards MT21 Replies
Altera_ForumDoes your LVDS block have the PLL, or are you creating it outside? If embedded, I think the multicycle constraints should automatically be done in the IP(or they get added when you run derive_pll_clocks). If there outside of the PLL, then in the Megawizard when you check this option, a pop-up comes on and tells you what multicycles to add. It doesn't do exact syntax or endpoints, since some of the registers are in your logic(I think). If you want to, make a side project, copy the LVDS blocks over and have them create the PLL. Throw them into a schematic and compile, and see what MCs are run when you do derive_pll_clocks.
