Constrainst for data launched by negative edge

Hello,

Here is what I would do if I am there.

(1) I would take one pll with following parameters:

-> Mode : Source synchronous mode ( https://www.altera.com/support/support-resources/operation-and-testing/pll-and-clock-management/pll-glossary.html#source_synchronous_mode )

-> Input clock : Clock which is coming from external device

-> Output clock 0 : With same frequency as input clock

(2) Then I would use pll's output clock 0 to sample incoming signals.

My SDC file would have following constraints :

# Base clock

create_clock -period "100MHz" -name CLK_IN [get_ports CLK_IN]

# Virtual clock

create_clock -name CLK_IN_VIRT -period "100MHz"

# Deriving PLL clocks

derive_pll_clocks

# Derive clock uncertainty

derive_clock_uncertainty

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -clock_fall -max $in_max_value [get_ports {DATA*}]

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -clock_fall -min $in_min_value [get_ports {DATA*}]

I have assumed here that incoming clock is continuous. is this correct?

I am learning these timing constraints. So, feel free to share your opinion if you have any concern.

Thank you,

Bhaumik