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Honored Contributor
Honored ContributorConstraining source syncronous output
Hi all, I'm trying to understand the constraining of source synchronous interfaces. I am a little bit confused. Let’s say we have an interface to an external SDR SDRAM device. The latch clock f...
Altera_ForumHonored Contributor
Honored ContributorI'm not sure which online training you've watched, but here are some specifically on this topic for others reading this:
https://www.altera.com/support/training/catalog.html?coursetype=online&keywords=source synchronous
