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Altera_Forum
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9 years ago

Constraining source syncronous output

Hi all, I'm trying to understand the constraining of source synchronous interfaces. I am a little bit confused. Let’s say we have an interface to an external SDR SDRAM device. The latch clock f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi GooGooCluster,

Thanks, I guess you are right.

I think i'm now at least able to choose the correct equations and the correct values for the different cases... Even if i don't understand why its called a delay ;)

best regards