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Altera_Forum's avatar
Altera_Forum
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13 years ago

Constraining ic delays

Hi all, I am synthesising my project and i am having timing violations wrt to IC delays. My cell delays are under control but dont know why even after adding a proper sdc the tool is not able ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok i get you...i know you strongly recommend virtual clock and i also tried using it but failed badly...I have two problems in understanding virtual clock that you have often suggested to many.

1. The advantage

2. If i am not feeding the clock to any port how will it constraint my design. How will the tool know the frequency it has to meet. I know that the problem lies with my understanding and thats why i couldnt use it although i really want to know the advantage of it.

I will also try your suggestion using input and output delays only to driving ports and can you also tell me the correct way of using pll I also tried using pll but maybe the correct syntax is wat i am failing in and yes one thing would like to mention that the reports are generated in ARRIA V.