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Altera_Forum
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14 years ago

Constraining ic delays

Hi all, I am synthesising my project and i am having timing violations wrt to IC delays. My cell delays are under control but dont know why even after adding a proper sdc the tool is not able ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

okk i got the 1st point but the tool has generated the report any problem with any other constrain..I mean i need the clock skew in the required path but yes its not there so what should i do about that.