Constraining ic delays

okkk i am sharing my sdc..but your first point was not clear to me..one thing that i can say wrt 2nd point is that the inputs and outputs are not registered so by virtual pin assignment the tool jus removes the last IC and buffer of the path. The rest of the path remains and yes the oExt is the set_output_delay and one more question you told me earlier that a skew of 3 to 4 ns is normal...but in the paths i have sent you even if my data delay was 0.1ns i cant meet timing because of the skew.