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Altera_Forum
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11 years ago

Constraining an SPI interface

Hello all, What is the proper way of constraining a 4-wire SPI master interface? I have several devices connected to my SPI bus, and fastest one can accecpt a SCLK up to 33 ns period, with setu...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Given that you're gating the SPI clock, I suspect you need to create another generated clock, and use that in all of your timing constraints.

Cheers,

Dave