Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Constrain a generated clock

I have a generated clock (derived from a PLL) that is used in the FPGA and also feeds an output pin. The clock is constrained using derive_pll_clocks TimeQuest reports the clock outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

I've added a create_generated_clock for the clk_out pin and also set a false path to the pin. TimeQuest no longer reports the output as being unconstrained, the code fully meets timing and runs correctly.

Thanks for your assistance.

--- Quote End ---

I don't know what this combination means or settles to! may be one takes priority over other by the the tool.

You also need to be careful about pass criteria. You should enter correct constraints then pass.