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Altera_Forum
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11 years ago

Constrain a generated clock

I have a generated clock (derived from a PLL) that is used in the FPGA and also feeds an output pin. The clock is constrained using derive_pll_clocks TimeQuest reports the clock outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I've added a create_generated_clock for the clk_out pin and also set a false path to the pin. TimeQuest no longer reports the output as being unconstrained, the code fully meets timing and runs correctly.

Thanks for your assistance.