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Honored Contributor
Honored ContributorConstrain a generated clock
I have a generated clock (derived from a PLL) that is used in the FPGA and also feeds an output pin. The clock is constrained using derive_pll_clocks TimeQuest reports the clock outp...
Altera_ForumHonored Contributor
Honored ContributorThe generated clk (from derive_pll_clocks) applies to PLL output. This is not seen as the clk_out pin which should be constrained separately as sourced from PLL output:
Here is altera example # Apply a generated clock to the clk_out port create_generated_clock -name clk_out -source [get_pins inst|altpll_component|pll|CLK[0]] [get_ports clk_out]
