Connecting of two FPGAs in synchronous mode.

Brad

First, thanks for the fast response.

I use a different technique to do the timing budjet. These are the facts that I count on:

1. All output FFs are located inside the pads, which means that I have ~2ns delay from FF to pad.

2. All input FFs are located inside the pads and I use the input delay element in the minimum option (~0.5ns) - this gives me ~2ns delay total

3. The trace on borad is ~3inch which is about 0.5ns

4. The PLLs are in normal mode which means that the clock is locked to the input pins - this ensures that the clock tree starts at the same timing point in all FPGAs

5. I've measured the clocks relation from FPGA to FPGA using a scope and they look very well - ~1ns phase shift.

So the total delay is 2n + 2n + 0.5n +-(1n) which is 3.5-5.5ns delay.

This gives me at least 6.5ns setup time.

I prefer to use this way since when I lock all the paramters, I will probably not have variation in the versions results.

Is it correct? Do you think it's better to use virtual clock and timing constraints?

Moti