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can I build FIR-like structures in FPGA to process multi-channels of high speed pulse train and detect less than 0.1ns delay between each pulse?
Not going to happen. Not in any existing FPGA. Would be difficult to do even in an ASIC.
If you design some logic, controlling the delays to such accuracy is not within the realm of existing layout tools.
You would need to go to a fully manual placement and routing.
And probably a spice-level timing simulation to validate your design works as expected.
The simple timing analyzer tools provided for FPGA timing analysis are insufficient for such an analysis.
Given the maximum clock rates in the 500MHz to 1GHz range you can not process 10GHz (ie, 100ps) signals.
The existing technology is one to two orders of magnitude slower than your requirement.
