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Honored Contributor
Honored ContributorConfiguring ADC using FPGA
I am trying to configure an ADC using an FPGA. I can read the default values from the ADC register properly, but I'm unable to write to those registers. The fpga clock is 48 MHz and serial clock ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Even though the ADC has a mode where chip-select can be asserted low all the time, it might need it to be deasserted while being powered up. --- Quote End --- Yes, the chip misses a means to reset the SPI protocol without deasserting CS. I don't see a reliable way to operate the device without connecting CS.
