Configuring active serial PROM and CPLD in single JTAG header chain

of course you can

make shure your fpga is the first in the jtag chain, otherwise you must tell all your scripts and tools to use device 2 what is a pain. if the fpga is the first in the row then you just connect the jtag to your pcb and quartus and all others run as there is only one device

in my designs i have

jtag tdo pin 3 <- MaxII TDO

MaxII TDI <- FPGA TDO

FPGA TDI <- JTAG tdi pin 9

so your cpld is the first device on jtag chain