Honored Contributor
Honored ContributorI performed another variation on the programming of the FPGA's. This time I UN-Checked the "Disable AS/AP mode CONF_DONE pin error check" check box.
in the Advanced menu of the "Convert Programming File" (CPF) utility. Also, I disabled the "Auto-restart the configuration after error" check box in the Devices Settings for the FPGA's and then recompiled them. This is what I got 4. Loaded the EPCS16 with this *.pof. Powered down. Powered back up. And ... a) No blinking lights, FPGA logic not running. b) nStatus LOW and pulsing. Not re-configuring. <<<< this time the Config Done error was detected and indicated by nStatus. c) nCEO Low and not toggling. d) Config_Done (OR'ed from both FPGA's) Low, not happy. e) Init_Done from first FPGA High, happy (?). <<<< Init_Done seems to indicate things are well but the FPGA logic is not running (?) 5. Attached USB Blaster to JTAG port for second FPGA and loaded second FPGA with its own *.sof. Info: Device 1 contains JTAG ID code 0x020F40DD Info: Configuration succeeded -- 1 device(s) configured Info: Successfully performed operation(s) Info: Ended Programmer operation at Mon Nov 04 09:57:52 2013 nStatus still Low. No change in signals from step (trial) 4. above. 6. Repeated the steps with the "Disable AS/AP mode CONF_DONE pin error check" check box checked and got the same results as before for this case. ================================================================================= My Speculations: 3. Init_Done is not valid unless nStatus is High. 4. A Config Done Error is probably being signaled by the second FPGA and by checking the "Disable AS/AP mode CONF_DONE pin error check" check box, the nStatus will not see this and go High at the end of the configuration cycle. 5. Programming via JTAG will not get things going if nStatus is indicating an error
