Configuring 2 Cyclone III's from one EPCS16 Using 2.5V

Thank you for your reply.

I do have nCE of the second device driven by the nCEO of the first device.

I believe you helped me pick the bus-switch when I was doing the schematics for the board.

I see the issue in your diagram, that the PS timing of the second FPGA has little or no margin.

I did not get the impact of this the last time I saw this.

I did measure my signals and have included images with this reply. The clock was measured with a nice

differential probe, but the data was measured with a standard probe with a long ground lead.

I really have very little margin on the PS as you suspected.

Q3: Do you know off the top of your head whether I can simply invert the clock to the second FPGA

to improve the PS Timing? I could use a NAND gate buffer instead of an AND.

I did notice that DCLK does not pause at the point where nCEO goes from inactive to active. DATA

however does not transition for an interval before and after the switch (nCEO going active). I

expect that there is a "start bit" in the DATA and the timing of the clock with respect to nCEO does

not matter. What do you think?

Much to my dismay the nStatus and Config_Done signals between the two FPGA run completely on

inner signal layers from one BGA via to the other BGA via.

Thanks again