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12. The Config_Done line does not even twitch off of zero Volts.
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If it did, we probably would not be having this conversation :)
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13. The nStatus line has a rise time (10% to 90%) of approx. 700 ns, and a fall time of about 1.5 ns.
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To be expected; its driven low, but tri-stated and pulled-up when going high.
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14. The INIT_DONE line will go high 448 ns after the nStatus line goes low, and goes low 115 us later, 60 us after nStatus goes high again.
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INIT_DONE is an optional pin, it only has meaning near the end of configuration.
Have a look at this doc, it has some INIT_DONE timing examples
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf --- Quote Start ---
15. nStatus goes low 800 ns before nCEO of the Master FPGA goes back high.
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Could you clarify; did nCEO transition from high-to-low, implying that the first FPGA configured ok, and its the second that causes the failure?
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16. From estimates made by my PCB CAD program, the delay of DCLK from FPGA to EPCS16 is 0.56 ns plus the translator delay. The delay of DATA_0 from the EPCS16 to the FPGA is 0.47 ns plus the translator delay. the translator delay from the datasheet is 0.15 ns max., but could actually be seen to be 1.5 ns. Round trip clock to data back is then about 1.5 + 1.5 + 0.56 + 0.47 = 4.03 ns.
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So do the math - is there any timing margin for the PS device?
Cheers,
Dave
Honored Contributor
