Honored Contributor
Honored ContributorMORE INFO FROM POSTER:
12. The Config_Done line does not even twitch off of zero Volts. 13. The nStatus line has a rise time (10% to 90%) of approx. 700 ns, and a fall time of about 1.5 ns. 14. The INIT_DONE line will go high 448 ns after the nStatus line goes low, and goes low 115 us later, 60 us after nStatus goes high again. 15. nStatus goes low 800 ns before nCEO of the Master FPGA goes back high. 16. From estimates made by my PCB CAD program, the delay of DCLK from FPGA to EPCS16 is 0.56 ns plus the translator delay. The delay of DATA_0 from the EPCS16 to the FPGA is 0.47 ns plus the translator delay. the translator delay from the datasheet is 0.15 ns max., but could actually be seen to be 1.5 ns. Round trip clock to data back is then about 1.5 + 1.5 + 0.56 + 0.47 = 4.03 ns.
