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AS configuration master of the two and IO_FPGA.sof is set as the PS configured slave FPGA
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So do you have the nCE of the second device driven by the nCEO of the first device?
I performed a timing analysis of this method, and technically it can fail to meeting timing, eg., see the attached.
The SN74CB3T1G125DBVR is a bus-switch, so you have selected the appropriate type of part to minimize the buffer delay.
You should measure the signals with a scope and compare them to the setup/hold time requirements in the attached.
If its possible to separate the nSTATUS signal and CONF_DONE signals for the two FPGAs, you could try configuring them individually. You could also try configuring them with JTAG to check that they do actually configure correctly. JTAG will only work if you configure them in sequence, so that nCEO from the first enables the second.
Cheers,
Dave
Honored Contributor
