Forum Discussion
Altera_Forum
Honored Contributor
13 years agoApparently, Quartus isn't prepared to implement a PFL virtual JTAG instance for FPGA targets. It should be possible, to port the MAX II PFL design to FPGA because it's pure readble HDL code.
I'm not sure, if the PFL functionality available with Cyclone III for configuration of the device itself can be used for an "external" PFL interface. But it may be possible.