Forum Discussion
Occasional ContributorConfig pins as normal IO pins
Well, for reference I have about two dozen Altera FPGA production designs I have done over that last two decades, and never have I reused the configuration/status pins as normal I/O, or the JTAG pins either. They are all dedicated to their specific functions. If I needed more I/O, I went to either a larger package with more I/O capability, or found some way to multiplex existing I/Os (like using an external 8bit shift register device as an I/O expander, for example). Again just my 2c.
Regular ContributorOk, so have you read: "Intel® MAX® 10 FPGA Configuration User Guide" (ug_m10_config.pdf) Chapter 3? Talks all about how to do this.
Occasional ContributorYes, I read it, but for me is a bit unclear.
Example: in "Table 3-1: Dual-Purpose Configuration Pin Guidelines for MAX 10 Devices" I read:
(for nConfig, nStatus, CONF_DONE) "During initialization:
• tri-state the external I/O driver and drive an external pull-up resistor(6) or
• use the external I/O driver to drive the pins to the state same as the external weak pullup resistor"
Whath exactly means?
I can't exactly distinguish user mode from initialization mode.
Aren't there any example circuits that show you how?
