Honored ContributorI am using a Cyclone III. Is there a possibility or has someone created a design to test that this whole thing is working correctly. In detail to test all the LE connections and so on... I know it must be a huge design but maybe someone has got something like this.
Thanks
Honored ContributorThere's no way to test everything with one design. LE's have many, mutually exclusive functions. Routing channels all have different switching paths, which can't all be on at the same time. You would need many, many, many designs to really test everything, plus a very complex methodology for proving out failures(what would a routing failure look like)? All chips are tested before Altera ships them. I have seen some users try something like this, i.e. make a huge design that runs through a ton of logic, but I have no idea if the coverage would be 10% or 90% or somewhere in between.
In reality, if you really want to check something, it's best to have a test that exercises your design in the part. That way you're testing what actually needs to be tested. (But in reality, I don't think that's even necessary under most situations...)Honored ContributorOk thanks,
as I heard from the ALTERA support, there might be a possibility to the check at least all the pins by BSDL?! Anyone already got some test to do so???Honored ContributorTesting IO's with boundary scan would be easy,at least with a boundary scan tester.I work with tools from JTAG Technologies,and it would be a matter of 5minutes to make a test like that,but it runs on their hardware.
But normally ,when you are in doubt about the integrity of a chip,it would be soldered on a board,wouldn't it? So you will need to know everything about this board (schematics,netlist,datasheet of all chips etc...).and then you can make a board test around your FPGA.You tell the tools which pins to drive high or low,which pins to sense 0 or 1 in order not to make any short circuits. and about the internals of the FPGA .... you just can't test it,that's true.I have a CycloneII chip here with defect internal RAM,all the rest is OK (or at least the parts that I use in that particular design)Honored ContributorIsn't there a way to load the FPGA step by step with a growing design to find out if it is a malfaunction of IOs oder internals? I once had the case that all worked - including IO behaviour - but when adding design parts which forced the fitter to aquire some more block RAM than before, the chip failed. Replacing the CHIP was the solution.
BTW: These problems lead me to demand allways more than only one board for testing, when loading designs into systems, which both are still under development :-)
