Complete FPGA Check

There's no way to test everything with one design. LE's have many, mutually exclusive functions. Routing channels all have different switching paths, which can't all be on at the same time. You would need many, many, many designs to really test everything, plus a very complex methodology for proving out failures(what would a routing failure look like)? All chips are tested before Altera ships them. I have seen some users try something like this, i.e. make a huge design that runs through a ton of logic, but I have no idea if the coverage would be 10% or 90% or somewhere in between.

In reality, if you really want to check something, it's best to have a test that exercises your design in the part. That way you're testing what actually needs to be tested.

(But in reality, I don't think that's even necessary under most situations...)