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Is there anyone consider the ramping time upon power-on for the core voltage
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The said datasheet notice is not addressing overshoots. The point is to avoid I/O voltage drops, particularly when the configuration pins are located in a bank not powered by the same supply as VCCA.
The power on reset is released, when VCCINT and VCCA have reached a specified level. If the IO voltage supplying configuration pins (MSEL, JTAG, PS, AS or AP related) isn't stable at this time, the configuration interface may take an unoperational state. That's it.
The problem may arise, if 3.3V and 2.5V supply are generated by different voltage regulators and 3.3V is delayed. If you in contrast generate 2.5V by an LDO from 3.3V, the issue should never be seen.
Honored Contributor
