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Altera_Forum's avatar
Altera_Forum
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13 years ago

combinational logic path timerequest slack

Hi, I encounter a time slack problem. In timequest i find the path between two registers is two long ,there are too many levels of combintional logic .so i locate the path in the technology map...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Not sure what you mean by it being translated to the bottom level. That is the place where it is coded, as there is no higher level translation. If you're going to insert pipeline registers, you have to understand the code, there's no way around that. Maybe the RTL viewer will help decipher it?

Are you using some high-level HDL generation tool? QSYS, Advanced DSP Builder or something like that? There is certainly a difficulty in understanding the low-level HDL, and most fixes for any issues here need to be done at the high-level.