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Altera_Forum
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7 years ago

Code works in functional simulation but not on the FPGA board

Greetings! I am working on a verilog code that generates the Lorenz chaotic attractor on the DE2-115 Altera FPGA board. My code generates new values for 3 variables at every posedge of the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Your screenshot got resized and it is unreadable.

There are too many things that might go wrong in this case, and it would be hard to diagnose the problem remotely. But, just for starters, can you tell if you are communicating with the board at all? That is, are you sure that you're reading zeros, as opposed to not receiving at all, because something is wrong on the PC side, or because the cord is unplugged, or because your FPGA design ends up sending the packets into pins that don't actually correspond to the UART interface?