Code works in functional simulation but not on the FPGA board

Greetings!

I am working on a verilog code that generates the Lorenz chaotic attractor on the DE2-115 Altera FPGA board.

My code generates new values for 3 variables at every posedge of the clock signal (u, v, w). These variables are represented using fixed point representation with each variable consisting of 32 bits.

Next, I am supposed to send the three 32-bit variables to a terminal PC using UART in order to plot a 3D graph on MATLAB.

Due to the limitation of the UART interface, it sends only 8 bits at a time, therefore, I try to packetize every variable into 4 packets each consisting of 8 bits and the send them one packet at a time such that within one clock cycle of u, v, w generation we transmit 12 packets that correspond to the 4 packets of each variable.

I have written a testbench to simulate this whole process, and the simulation works perfectly fine with packets being packetized correctly and then transmitted serially through the UART interface.

Now the problem is whenever I flash the code onto my FPGA board and try to run it instead of receiving correct packets I receive only zeros.

Please find attached a screenshot of the whole simulation.

Could you please help me out or guide me through this problem?

Thanks a lot!