code problem

Is it a model of the asynchronous DRAM?

Is it only behavioural model? So you do not suppose to synthesize this architecture? Because for only behavioral check this architecture could be OK. But you should specify a delay on each gate to simulate the behaviour properly, because these ones:

add_en_next<='0';

used(num)<='1';

data_array(num)(15 downto 8)<=H_Dn;

data_array(num)(7 downto 0)<=H_GD;

Will happen almost simultaneously, the only difference - different delta cycles in the simulator.

If you want to synthesise this stuff, it would generate not safe latches with glitches possibility. For synthesis in FPGAs you have to use the RTL style of coding.