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Altera_Forum
Honored Contributor
Honored ContributorCode is not synthesized as expected
Hi all, I have a code for registers configuration, in this code there is a "cpu interface" component which writes/reads to/from registers. The "cpu interface" drives a "cpu_wr" signal which is sent t...
Altera_ForumHonored Contributor
Honored ContributorThe wr signal goes to areas of logic:
1) it goes to AND logic followed by registering data into int_Q then another register into out_Q (clked process) 2) it goes to the logic for data <= out_Q (combinatorial) then goes to unknown... I wouldn't worry about looking into fitting result (at least your picture is too hard to see details). It is likely the second path is failing You will need to identify specifically which path is failing. Regarding bidirectional bus, this will be converted to muxes and the paths will follow accordingly.
