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Altera_Forum's avatar
Altera_Forum
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11 years ago

Code is not synthesized as expected

Hi all, I have a code for registers configuration, in this code there is a "cpu interface" component which writes/reads to/from registers. The "cpu interface" drives a "cpu_wr" signal which is sent t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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The post is ok for this forum. I wouldn't suspect synthesis is the cause of timing failure unless proved otherwise. So let us focus on timing reports

what does it actually report? is it setup violation,hold violation and which paths (internal or io). can you also post the code for those register modules.

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O.K thnaks, The report is for setup violation, the code is attached. Hope you will be able to explain why the "write" port goes through other registers on its way to the destination register, maybe becasue it has bidirectional data port?