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Altera_Forum's avatar
Altera_Forum
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11 years ago

Code is not synthesized as expected

Hi all, I have a code for registers configuration, in this code there is a "cpu interface" component which writes/reads to/from registers. The "cpu interface" drives a "cpu_wr" signal which is sent t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Say you failed timing but you think synthesis failed. Am I right?

If it is due to fan out then you can duplicate as many registers for wr as you want.

But it is more helpful to present the problem as reported by tool.

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Well, the Timequest timinig analyzer reports for failing path but this is just a warning, the synthesis is finished succesfully with- "Critical Warning: Timing requirements not met". My problem is not just the warning, i opened the thread in order to understant the attached synthesis for the attached code. Should i open it under another forum?