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roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Clock synthesis and de-skewing using an IOPLL in Arria 10

I'm trying unsuccessfully to use an IOPLL to synthesize a clock and have it be in-phase with the reference clock, where both the reference clock and the synthesized clock are routed on GCLKs. By "in-...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

The PLL can compensate for the clocks that are generated by it, not other network path. Though both clk1 and clk2 are driven by the GCLK network, they may be placed far away (you may find out from the ChipPlanner).

You may experiment with the scenario that I explained in my previous answer. Generate both clk1 and clk2 from same PLL. That will definitely give you better result.

I did these experiments on a simple design and suggesting them based on those.


Regards.