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roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Clock synthesis and de-skewing using an IOPLL in Arria 10

I'm trying unsuccessfully to use an IOPLL to synthesize a clock and have it be in-phase with the reference clock, where both the reference clock and the synthesized clock are routed on GCLKs. By "in-...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Sorry for the late response. One thing that I want to point out from your report is that the incoming clock is fed to the CLKCTRL block for some reason. Does the the CLKCTRL block has two fanouts, PLL and core logic?

If yes, then that might be the issue. The PLL will not be able to compensate for the network that is fed by the incoming clock. You may want to generate a same frequency clock from PLL to operate. I think the set_max_skew constraint should also be set between the two clock domains.


If the CLKCTRL block is driving only the PLL, then it can be avoided. Use dedicated clock pin to feed the PLL directly.


Regards