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Altera_Forum's avatar
Altera_Forum
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15 years ago

clock structure?

The cyclone ii fpga handbook says it has 4 built in PLLs. Are these associated with a particular input pin on the device? Is one of the main advantages of using a PLL on a clock input to increase acc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ok thanks.

so if I have a design in which the clock is routed into a general I/O pin (not one of the 16 clock pins), but do not need to use the PLL, will this be problematic?