--- Quote Start ---
I actually have a double clocked register wr_d2 but I was wondering if its really that critical.
--- Quote End ---
Yes, correct synchronization is very critical.
--- Quote Start ---
What is the advantage of putting it into a sync component?
--- Quote End ---
Well written code should be easy to read. If you have to synchronize a lot of input signals, then you'll have ale, ale_d1, ale_d2, etc. If you have a synchronizer component, then you'll just have two signals, i.e., ale and ale_sync.
--- Quote Start ---
I'm not quite sure how this would shift the edge 1/2 clk.
--- Quote End ---
It doesn't. The objective was to create a signal that pulsed for one clock period in the FPGA clock domain for each (asynchronous) ALE pulse.
--- Quote Start ---
I assume you meant something like:
assign wr_edge = (wr_d2 && !wr_d3);
or should I clock it into a register? (it does not seem to matter, other than it delays it one more cycle).
--- Quote End ---
Yeah, something like that. Whether or not it needs to be clocked depends on what that pulse feeds. Since the original signal was asynchronous, there's no harm in adding the output register to reduce the combinatorial path lengths.
Cheers,
Dave
Honored Contributor
